1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory and a control device using the same, and more specifically, to a technology wherein data stored in a page address buffer are immediately outputted without accessing a memory cell in page address access operation.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as “FRAM”) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents on the above FRAM are disclosed in the Korean Patent Application No. 2002-85533 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FRAM are not described herein.
The access operation of the conventional nonvolatile ferroelectric memory is controlled by the configuration of FIG. 1.
The conventional nonvolatile ferroelectric memory control device comprises a chip enable signal buffer 1, an address buffer 2, a decoder 3, a chip enable signal transition detector 4, an address transition detector 5, a synthesizer 6 and a chip control signal generator 7.
The chip enable signal buffer 1 buffers a chip enable signal CEB_PAD inputted from a pad, and outputs a chip enable signal CEB. The address buffer 2 buffers addresses ADD_PAD<m:0> inputted from the pad in response to the chip enable signal CEB, and outputs the buffered addresses. The decoder 3 decodes the addresses buffered in the address buffer 2.
The chip enable signal transition detector 4 detects transition of the chip enable signal CEB, and outputs a chip enable transition detecting signal CTD. The address transition detector 5 detects transition of the addresses buffered in the address buffer 2, and outputs address transition detecting signals ATD<m:0>.
The synthesizer 6 synthesizes the chip enable transition detecting signal CTD and the address transition detecting signal ATD, and outputs a transition synthesizing signal ATD_S. The chip control signal generator 7 selectively generates chip control signals for driving a memory chip as the chip enable signal CEB and the transition synthesizing signal ATD_S applied from the synthesizer 6.
However, the conventional nonvolatile ferroelectric memory device whose operation is controlled by the control signals requires more improved reliability when it is used in a SOC (System On Chip) structure or a stand-alone structure.
If a voltage is frequently applied to a FeRAM cell, the cell also frequently operates. As a result, power consumption increases, thereby degrading reliability.
Since the conventional nonvolatile ferroelectric memory control device comprises row addresses and column addresses arranged at random, power is consumed unnecessarily when the FeRAM cell is driven. Thus, the unnecessary operation of the memory cell applies excessive stress to the cell, which results in reduction of life span of the cell.